1. Field
Exemplary embodiments of the present invention relate to a semiconductor device for generating a reference current, and more particularly, to a technology for offset compensation of a reference current.
2. Description of the Related Art
A reference voltage generator generates a reference voltage that is used as a reference power source in a semiconductor memory device. Generally, the reference voltage generator receives an external voltage and generates an internal voltage whose level is lower than the level of the external voltage.
Semiconductor memory devices tend to operate at low voltage and consume low power. An internal voltage generator receives a high external voltage that is inputted from the outside of a semiconductor memory chip and generates an internal voltage level that is used in the semiconductor memory chip, in order to reduce the power consumption of the semiconductor memory chip while improving the operation performance of the semiconductor memory chip.
In particular, in the field of high-density memory devices, an internal voltage down-converter using an external power supply VDD is being used. The internal voltage down-converter is used as a voltage source for an internal circuit. The internal voltage down-converter generates a low level voltage thus reducing the power consumption of a semiconductor memory device and preventing the life-span of a device from being shortened due to high voltage stress.
However, the current-voltage characteristics of a P-type metal-oxide semiconductor (PMOS) transistor, which is provided as an active load in a conventional voltage down-converter, changes due to an external factor such as a variation in a process. Even in a slight change in the characteristics, the output voltage of the PMOS transistor may change in response to the same level of the input voltage thereof. This signifies that the generated internal voltage may be different for each chip, even though the circuit of the same structure is used.
FIG. 1 is a circuit diagram illustrating a typical Widlar-type reference voltage generator. The reference voltage generator generates a reference voltage VREF of a constant level based on an external power supply voltage VDD and a ground voltage VSS.
Referring to FIG. 1, when the power supply voltage VDD is applied, a reference voltage node outputs a reference voltage VREF decreasing from the power supply voltage VDD by a threshold voltage of a second PMOS transistor MP2 because the second PMOS transistor MP2 operates as a diode.
Since the reference voltage node is coupled with a gate of a first PMOS transistor MP1, the first PMOS transistor MP1 is turned on in response to the voltage level VDD-VTH of the reference voltage node and transfers a current of a certain amount to a node A.
The second negative-channel metal-oxide semiconductor (NMOS) transistor MN2 is also diode-coupled. Thus, at the reference voltage node coupled with a drain of the second PMOS transistor MP2, clamping occurs at a level equal to or higher than the threshold voltage of the second NMOS transistor MN2.
The reference voltage node is coupled with the gates of first NMOS transistors MN1A, MN1B and MN1C so as to form a great resistor, and the first NMOS transistor MN1 is coupled with a resistor R0 to make temperature compensation.
While a current flows through a conductor in inverse proportion to temperature, the current flows through a semiconductor in proportion to temperature.
Therefore, it is possible to detect a zero temperature coefficient at which the current is not affected by temperature.
When the first NMOS transistor MN1 is not turned on, the first NMOS transistor MN1 functions as a semiconductor or a nonconductor, and when the first NMOS transistor MN1 is turned on, the first NMOS transistor MN1 functions as a conductor. Therefore, the first NMOS transistor MN1 may develop a temperature compensation effect in combination with the load R0, which is a substantial conductor.
The Widlar-type reference voltage generator, which described above, is typically used in memory devices and other CMOS-based devices.
Generally, a current having a constant level irrelevant to the variation of PVT (Process, Voltage, and Temperature) is referred to as a reference current.
As described above, in order to generate the reference current and maintain its characteristics as a reference, there is to be no local mismatch between transistors and the characteristics of the transistors used in a current mirror should be the same.
In general processes, however, there is a mismatch between the characteristics of mirror transistors that are used in a current mirror, and an offset, i.e., a deviation from a target value, occurs in a sensitive current mirror-type circuit. Therefore, the reference current may not be generated stably.
The offset of a circuit deteriorates the characteristics of the reference current, and increases the possibility of erroneous operation to occur, thus adversely affecting mass-productivity of a chip and product reliability.